1. Field of the Invention
The present invention generally relates to a method of fabricating a semiconductor device, and more specifically, it relates to a method of fabricating a BiCMOS (Bipolar-Complementary Metal Oxide Semiconductor) device having a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor. The present invention also relates to a semiconductor device obtained by this method.
2. Description of the Prior Art
A BiCMOS device provided with both of a bipolar transistor having high-speed performance and excellent drivability and CMOS transistors allowing high integration and having low power consumption is generally employed as a semiconductor device.
FIG. 82 is a sectional view of a conventional BiCMOS device.
First, a bipolar transistor part is described.
An N+-type embedded layer 3 is formed on a P-type silicon substrate 1, and an N-type epitaxial layer 4 is further formed on the upper surface thereof. A field oxide film 7, a P-type well region 12 and a P-type isolation region 5 are formed for element isolation. A base region, consisting of a P-type intrinsic base region 16 and a P+-type external base region 18, and an N+-type emitter region 19 are formed on a surface part of the N-type epitaxial layer 4. The field oxide film 7 is held between an N+-type collector region 2 and the epitaxial layer 4. The N+-type collector region 2 reaches the N+-type embedded layer 3.
A P+-type external base draw-out electrode 13 is provided on the external base region 18. The external base draw-out electrode 13 extends onto the field oxide film 7. An N+-type emitter electrode 20 is formed in an emitter opening of the external base draw-out electrode 13. The emitter electrode 20 and the external base draw-out electrode 13 are electrically isolated from each other by side wall oxide films 17 and an oxide film 14. An interlayer isolation film 32 covers the external base draw-out electrode An interlayer isolation film 32 covers the external base draw-out electrode 13, the emitter electrode 20 and the N+-type collector region 2. Contact holes 6 are formed in the interlayer isolation film 32. Metal wires 33 (aluminum wires, for example) are formed in the contact holes 6.
CMOS transistor parts are now described.
First, a PMOS (P channel Metal Oxide Semiconductor) part is described. An N+-type embedded layer 3 is formed on the P-type silicon substrate 1. An N-type well region 10 is formed on the upper surface of the N+-type embedded layer 3. A field oxide film 7 is formed for element isolation. A gate electrode 22 (N+-type polysilicon film, for example) is formed on the surface of the N-type well region 10. P+-type source/drain regions 31 are formed on the surface of the N-type well region 10 on both sides of the gate electrode 22. The interlayer isolation film 32 covers the P+-type source/drain regions 31 and the gate electrode 22. Contact holes 6 are formed in the interlayer isolation film 32. Metal wires 33 (aluminum wires, for example) are formed in the contact holes 6.
An NMOS (N channel Metal Oxide Semiconductor) part is now described. A P-type isolation region 5 is formed on the P-type silicon substrate 1. A P-type well region 12 is formed on the upper surface of the P-type isolation region 5. A field oxide film 7 is formed for element isolation. A gate electrode 22 (N+-type polysilicon film) is formed on the surface of the P-type well region 12. N+-type source/drain regions 30 are formed on the surface of the P-type well region 12 on both sides of the gate electrode 22. The interlayer isolation film 32 covers the N+-type source/drain regions 30 and the gate electrode 22. Contact holes 6 are formed in the interlayer isolation film 32. Metal wires 33 (aluminum wires, for example) are formed in the contact holes 6.
A method of fabricating the BiCMOS device shown in FIG. 82 is now described.
Referring to FIG. 70, the N+-type embedded layers 3, the P-type isolation regions 5, the N-type epitaxial layer 4, the field oxide films 7 and the N+-type collector region 2 are formed on the P-type silicon substrate 1. Then, an underlayer oxide film 8 is formed on the surface of the silicon substrate 1. The thickness of the underlayer oxide film 8 is 30 nm, for example. A resist mask 9 is formed on the silicon substrate 1 by patterning. N-type impurities 111 are implanted into a region for forming a PMOS transistor through the resist mask 9. The impurities are implanted in a divided manner (phosphorus is implanted at 400 KeV by 2xc3x971012 cmxe2x88x922 and at 180 KeV by 4xc3x971012 cmxe2x88x922 and boron is implanted at 20 KeV by 3xc3x971012 cmxe2x88x922, for example) for forming the N-type well region 10 (see FIG. 71). Thereafter the resist mask 9 is removed.
Referring to FIG. 71, a resist mask 11 is formed on the silicon substrate 1 by patterning. A P-type impurity 222 is implanted into a region for forming an NMOS transistor through the resist mask 11, thereby forming the P-type well region 12 (see FIG. 72). Also in this case, the impurity is implanted in a divided manner (boron is implanted at 300 KeV by 1xc3x971012 cmxe2x88x922, at 160 KeV by 3xc3x971012 cmxe2x88x922 and at 50 KeV by 6xc3x971012 cmxe2x88x922, for example). Thereafter the resist mask 11 is removed.
Referring to FIGS. 71 and 72, the underlayer oxide film 8 is removed and a polysilicon film 13 is deposited on the overall surface by 150 nm, for example, and a P-type impurity is implanted into the polysilicon film 13 (BF2 is implanted at 40 KeV by 4xc3x971015 cmxe2x88x922, for example). Then, a CVD (Chemical Vapor Deposition) oxide film 14 is deposited on the overall surface by 300 nm, for example.
Referring to FIGS. 72 and 73, the CVD oxide film 14 and the polysilicon film 13 are patterned by etching, for forming the external base electrode 13. At this time, the surfaces of the collector region 2, the emitter opening, the N-type well region 10 and the P-type well region 12 are etched. Referring to FIG. 73, symbols A-1, B-1, C-1 and D-1 denote the collector region 2, the emitter opening, the N-type well region 10 and the P-type well region 12 respectively.
Referring to FIG. 74, a resist mask 15 is formed on the silicon substrate 1 by patterning. A P-type impurity 333 is implanted into the emitter opening (BF2 is implanted at 25 KeV by 8xc3x971013 cmxe2x88x922, for example) through the resist mask 15, for forming the intrinsic base region 16 (see FIG. 75).
Referring to FIG. 75, a CVD oxide film (not shown) is formed on the overall upper surface of the silicon substrate 1 and dry-etched, for forming the side wall oxide films 17 in the emitter opening.
Referring to FIG. 76, a polysilicon film for defining the emitter electrode 20 is deposited on the overall surface by 150 nm, for example, and an N-type impurity is implanted into this polysilicon film (arsenic is implanted at 50 KeV by 1xc3x971016 cmxe2x88x922, for example). After this impurity implantation, annealing is performed for diffusing arsenic into the intrinsic base region 16 from the polysilicon film, thereby forming the emitter region 19. At this time, boron diffuses from the external base electrode 13, for forming the external base region 18.
While diffusion of boron takes place also in heat treatment preceding this annealing step, such diffusion is not illustrated. Then, the polysilicon film is etched for forming the emitter electrode 20. At this time, the surfaces of the collector region 2, the N-type well region 10 and the P-type well region 12 are etched. Referring to FIG. 76, symbols A-2, C-2 and D-2 denote the collector region 2, the N-type well region 10 and the P-type well region 12 respectively.
Referring to FIG. 77, gate oxide films 21 are formed in a thickness of 10 nm, for example. Thereafter an N-type polysilicon film for defining the gate electrodes 22 is formed on the overall surface by 300 nm, for example. Then, the N-type polysilicon film is patterned for forming the gate electrodes 22. At this time, the thin oxide films 21 are formed on the surfaces of the N-type well region 10, the P-type well region 12 and the emitter electrode 20, so that the N-type well region 10, the P-type well region 12 and the emitter electrode 20 are not etched due to the difference between the etching rates for silicon and an oxide film (the etching rate for an oxide film is smaller than that for silicon).
Referring to FIG. 78, a resist mask 23 is formed on the silicon substrate 1 by patterning, and an N-type impurity 444 is implanted into the region for forming the NMOS transistor. For example, phosphorus is implanted at 70 KeV by 1.8xc3x971013 cmxe2x88x922 through 45xc2x0 rotational implantation, for example. Thus, Nxe2x88x92-type source/drain regions 25 are formed (see FIG. 79). Thereafter the resist mask 23 is removed.
Referring to FIG. 79, a resist mask 24 is formed by patterning for implanting a P-type impurity 555 into the region for forming the PMOS transistor (boron is implanted at 10 KeV by 1xc3x971013 cmxe2x88x922 through 7xc2x0 rotational implantation, for example), for forming Pxe2x88x92-type source/drain regions 26 (see FIG. 80). Thereafter the resist mask 24 is removed.
Referring to FIG. 80, a CVD oxide film is deposited and dry-etched, for forming side wall oxide films 27 on the side walls of the gate electrodes 22. Then, a resist mask 28 is formed by patterning and N-type impurities 666 are implanted into the region for forming the NMOS transistor (phosphorus is implanted at 100 KeV by 2xc3x971014 cmxe2x88x922 through 60xc2x0 rotational implantation and arsenic is implanted at 50 KeV by 4xc3x971015 cmxe2x88x922, for example), for forming the N+-type source/drain regions 30 (see FIG. 81). Thereafter the resist mask 28 is removed.
Referring to FIG. 81, a resist mask 29 is formed by patterning, and a P-type impurity 777 is implanted into the region for forming the PMOS transistor (BF2 is implanted at 40 KeV by 4xc3x971015 cmxe2x88x922, for example) through the resist mask 29, for forming the P+-type source/drain regions 31 (see FIG. 82).
Thereafter the resist mask 29 is removed.
Referring to FIG. 82, the interlayer isolation film 32 is formed on the silicon substrate 1. The contact holes 6 are formed in the interlayer isolation film 32 for defining openings on the emitter region 20, the external base electrode 13, the N+-type collector region 2, the source/drain regions 30 and 31 and the gate electrodes 22. The metal wires 33 are embedded in the contact holes 6, thereby completing the BiCMOS device.
The depths of the diffusion layers such as the emitter region 19 formed by diffusion of arsenic from the emitter electrode 20, the external base region 18 formed by diffusion of boron from the external base electrode 13, the intrinsic base region 16 and the source/drain regions 30 and 31 are decided by heat treatment performed for completing the device.
In the conventional method of fabricating a BiCMOS device, however, the surface parts of the well regions 10 and 12 of the CMOS transistors are remarkably scraped off due to etching for forming the external base electrode 13 and the emitter electrode 20, as shown in FIGS. 73 and 76. In other words, the N-type well region C-1, the P-type well region D-1 as well as the N-type well region C-2 and the P-type well region D-2 are remarkably scraped off. The scraped surface parts of the well regions C-1, D-1, C-2 and D-2 include implantation regions for adjusting threshold voltages Vth and drain-to-source currents Ids of the CMOS transistors. Boron 111 for forming the N-type well region 10 and boron 222 for forming the P-type well region 12 are implanted into the implantation regions at 20 KeV by 3xc3x971012 cmxe2x88x922 and at 50 KeV by 6xc3x971012 cmxe2x88x922 respectively. However, the characteristic values cannot be adjusted as designed since the surface parts are scraped off.
Even if swelling caused by etching is previously estimated for implanting boron, homogeneity of etching rates is deteriorated and extremely hard to control since etching is performed twice.
Further, the surfaces of the well regions 10 and 12 of the CMOS transistor parts are so inferior in flatness that it is difficult to uniformalize the thickness of the gate oxide film 21. Thus, the withstand voltage of the gate oxide film 21 as well as the characteristics such as the threshold voltages Vth and the drain-to-source currents Ids are dispersed, and the reliability of the gate oxide film 21 is deteriorated.
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a method of fabricating a semiconductor device so improved as to exhibit no dispersion of the withstand voltage of a gate oxide film.
Another object of the present invention is to provide a method of fabricating a semiconductor device so improved as to exhibit no dispersion of characteristics such as a threshold voltage and a source-to-drain current.
Still another object of the present invention is to provide a method of fabricating a semiconductor device improved to be capable of improving the reliability of a gate oxide film.
A further object of the present invention is to provide a semiconductor device fabricated by such a method.
A first aspect of the present invention relates to a method of fabricating a semiconductor device having a bipolar transistor and a field-effect transistor formed on a semiconductor substrate. First, a first oxide film for defining a gate oxide film and a first conductor film for defining a lower portion of a gate electrode are successively formed on the semiconductor substrate formed with a collector region. The aforementioned first conductor film and the aforementioned first oxide film are selectively etched for exposing a surface portion of the aforementioned semiconductor substrate located on a region for forming the aforementioned bipolar transistor. A second conductor film for defining an external base electrode and an upper portion of the gate electrode are formed on the aforementioned semiconductor substrate to come into contact with the aforementioned exposed surface portion and cover a region for forming the aforementioned field-effect transistor and the aforementioned collector region. A second oxide film is formed on the aforementioned semiconductor substrate to cover the aforementioned second conductor film. The aforementioned second conductor film and the aforementioned second oxide film are selectively etched for exposing a surface portion of the aforementioned semiconductor substrate thereby opening an emitter region. A third conductor film for defining an emitter electrode is formed on the aforementioned second oxide film to come into contact with the aforementioned emitter region. The aforementioned third conductor film is patterned for forming the emitter electrode on the aforementioned semiconductor substrate. The aforementioned second oxide film, the aforementioned second conductor film and the aforementioned first conductor film are patterned for simultaneously forming the external base electrode and the gate electrode.
According to a preferred embodiment of this aspect, the aforementioned step of patterning the aforementioned second oxide film, the aforementioned second conductor film and the aforementioned first conductor film for simultaneously forming the aforementioned external base electrode and the aforementioned gate electrode includes a step of first removing the aforementioned second oxide film located on the aforementioned external base electrode and the aforementioned gate electrode by etching and thereafter patterning the aforementioned second conductor film and the aforementioned first conductor film for simultaneously forming the external base electrode and the gate electrode.
According to another preferred embodiment of this aspect, the method of fabricating a semiconductor device further comprises a step of partially removing the aforementioned second conductor film by etching around a portion for defining the aforementioned external base electrode after forming the aforementioned second conductor film in advance of forming the aforementioned second oxide film.
A second aspect of the present invention relates to a method of fabricating a semiconductor device having a bipolar transistor and a field-effect transistor formed on a semiconductor substrate. First, a first oxide film for defining a gate oxide film and a first conductor film for defining a lower portion of a gate electrode are successively formed on the semiconductor substrate formed with a collector region. The aforementioned first conductor film and the aforementioned first oxide film are selectively etched for exposing a surface portion of the aforementioned semiconductor substrate located on a region for forming the aforementioned bipolar transistor. A second conductor film for defining an external base electrode and an upper portion of the gate electrode is formed on the aforementioned semiconductor substrate to come into contact with the aforementioned exposed surface portion and cover a region for forming the aforementioned field-effect transistor and the aforementioned collector region. A second oxide film is formed on the aforementioned semiconductor substrate to cover the aforementioned second conductor film. The aforementioned second conductor film and the aforementioned second oxide film are selectively etched for opening an emitter region while simultaneously partially removing the aforementioned second conductor film by etching around a portion for defining the external base electrode thereby forming the aforementioned external base electrode. A third conductor film for defining an emitter electrode is formed on the aforementioned second oxide film to come into contact with the aforementioned emitter region. The aforementioned third conductor film is patterned for forming the emitter electrode on the aforementioned semiconductor substrate. The aforementioned second oxide film, the aforementioned second conductor film and the aforementioned first conductor film are patterned for forming the gate electrode.
According to a preferred embodiment of this aspect, the aforementioned semiconductor substrate is annealed after simultaneously forming the aforementioned external base electrode and the aforementioned gate electrode.
According to another preferred embodiment of this aspect, the aforementioned second conductor film is patterned to simultaneously form a resistive element in the step of patterning the aforementioned second oxide film, the aforementioned second conductor film and the aforementioned first conductor film.
According to still another preferred embodiment of this aspect, the aforementioned third conductor film is patterned to simultaneously form a resistive element in the step of patterning the aforementioned third conductor film for forming the emitter electrode on the aforementioned semiconductor substrate.
According to a further preferred embodiment of this aspect, the method of fabricating a semiconductor device further comprises a step of forming a silicide film on a surface of the aforementioned emitter electrode, a surface of the aforementioned external base electrode, a surface of the aforementioned gate electrode and a surface of a source/drain region of the aforementioned field-effect transistor.
A third aspect of the present invention relates to a method of fabricating a semiconductor device having a bipolar transistor and a field-effect transistor formed on a semiconductor substrate. A first oxide film for defining a gate oxide film and a first conductor film for defining a lower portion of a gate electrode are successively formed on the semiconductor substrate formed with a collector region. The aforementioned first conductor film and the aforementioned first oxide film are selectively etched for exposing a surface portion of the aforementioned semiconductor substrate located on a region for forming the aforementioned bipolar transistor. A second conductor film for defining an external base electrode and a lower portion of the gate electrode is formed on the aforementioned semiconductor substrate to come into contact with the aforementioned exposed surface portion and cover a region for forming the aforementioned field-effect transistor and the aforementioned collector region. A second oxide film is formed on the aforementioned semiconductor substrate to cover the aforementioned second conductor film. The aforementioned second conductor film and the aforementioned second oxide film are selectively etched for opening an emitter region. A third conductor film for defining an emitter electrode is formed on the aforementioned second oxide film to come into contact with the aforementioned emitter region. The aforementioned third conductor film is patterned for forming the emitter electrode on the aforementioned semiconductor substrate. The aforementioned second oxide film located on the aforementioned external base electrode and the aforementioned gate electrode is removed by etching. The aforementioned second conductor film and the aforementioned first conductor film are patterned for simultaneously forming the external base electrode, the gate electrode and a resistive element. An insulator film is formed on a partial surface of the aforementioned resistive element. A silicide film is formed on a surface of the aforementioned collector region, a surface of the aforementioned emitter electrode, a surface of the aforementioned external base electrode, a surface of the aforementioned gate electrode and a surface of a source/drain region of the aforementioned field-effect transistor.
A fourth aspect of the present invention relates to a semiconductor device having a bipolar transistor and a field-effect transistor formed on a semiconductor substrate. The semiconductor device comprises the semiconductor substrate formed with a collector region. An emitter electrode, an external base electrode and a gate electrode are formed on the aforementioned semiconductor substrate. The position of the interface between the aforementioned gate electrode and the aforementioned semiconductor substrate is rendered higher than the position of the interface between the aforementioned external base electrode and the aforementioned semiconductor substrate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.